1. Field of the Invention
The present invention generally relates to data determining circuitry and a data determining method for determining the level of a data line used in a semiconductor circuit system. More particularly, the invention relates to current-mode-sense-type data determining circuitry for determining the level of a data line by detecting a current flowing in a drive circuit for the data line. The invention is also concerned with a data determining method used for the above type of circuitry.
2. Description of the Related Art
As a method for transferring data in a large scale integrated circuit (LSI) a current-mode transfer method is known and is becoming popular, since current-to-voltage conversion and low-amplitude high-speed transfer are possible in this method. For example, in a semiconductor memory circuit system, the current mode transfer is employed in a sense amplifier. Advantageously, in the current mode sense type, precharging is not required during the reading operation.
FIG. 4 is a schematic diagram illustrating the concept of a current mode sense amplifier. In FIG. 4, a P-type MOSFET (hereinafter referred to as "the PMOS") Trp31 and an N-type MOSFET (hereinafter referred to as "the NMOS") Trn31 are connected in series to each other between a power supply VDD and one end of a bit line 31. More specifically, the source electrode of the PMOS Trp31 is connected to the power supply VDD, while the source electrode of the NMOS Trn31 is connected to one end of the bit line 31. The drain electrode of the PMOS Trp31 is connected to the drain electrode of the NMOS Trn31, thereby forming a node N31. A sense output is extracted from the node N31.
The PMOS Trp31 is configured to act as a diode in which the gate electrode and the drain electrode are connected. The PMOS Trp31 is equivalent to a resistor which is offset by an amount equal to a threshold. Further, a reference voltage Vref is applied to the gate electrode of the NMOS Trn31. A memory cell 32 is connected between the other end of the bit line 31 and a ground GND. The memory cell 32 has the function of determining whether or not a current is caused to flow to the GND according to the state of the data stored in the memory cell 32.
In the circuitry configured as described above, it is now assumed that the memory cell 32 causes a current I to flow to the GND. In this case, the potential VBL of the bit line 31 decreases, increasing the gate-source voltage Vgs of the NMOS Trn31. This elevates the current capacity of the NMOS Trn31, thereby decreasing the drain-source voltage Vds. Namely, the NMOS Trn31 acts as a negative resistor in which the required applied voltage is decreased by causing a current to flow.
In this manner, since the PMOS Trp31 serves as a resistor, while the NMOS Trn31 acts as a negative resistor, the following condition is satisfied. EQU Vds (Trp31)+Vds (Trn31).apprxeq.constant
Accordingly, the potential of the bit line 31 remains almost unchanged regardless of the presence or the absence of the current I. The current-versus-output voltage characteristics of this circuitry are shown in FIG. 5. In this characteristic diagram, VN31 represents the potential of the node N31.
The above-described circuitry presents the following problem. It is difficult to maintain the potential of the bit line 31 at a constant level without a large transconductance gm of the NMOS Trn31. Consequently, the circuitry is configured in the following manner in order to maintain the potential of the bit line 31 at a constant level if the transconductance gm of the NMOS Trn31 is small. Such a circuitry configuration is shown in FIG. 6.
In FIG. 6, the same elements as those shown in FIG. 4 are designated with like reference numerals. The circuitry illustrated in FIG. 6 is similar to the counterpart shown in FIG. 4, except that a bias circuit 33 is newly inserted between the gate electrode of the NMOS Trn31 and the bit line 31. In this circuitry, the bias circuit 33 has a feedback bias mechanism that increases the potential of the output with a decreasing potential VBL of the bit line 31. A specific example of the bias circuit 33 is shown in FIG. 7.
In FIG. 7, the bias circuit 33 is formed of a PMOS Trp32, an NMOS Trn32, and an offset power supply 34. The PMOS Trp32 is connected at its source electrode to a power supply VDD and at its gate electrode to the bit line 31. The NMOS Trn32, which acts as a diode, is connected at its drain electrode to the drain electrode of the PMOS Trp32, at its source electrode to a ground GND, and at its gate electrode to the gate electrode of the NMOS Trn31. The offset power supply 34 is connected between the bit line 31 and a GND.
The operation of the foregoing circuitry is described with reference to the waveform diagram of FIG. 8. A decrease in the potential VBL of the bit line 31 causes a decrease in the potential of the gate electrode of the PMOS Trp32, thereby elevating the current capacity of the PMOS Trp32. This further increases the reference voltage Vref, which is applied to the gate electrode of the NMOS Trn31, and accordingly, the current capacity of the NMOS Trn31 is elevated, thereby limiting the decrease in the potential VBL of the bit line 31.
Conversely, an increase in the potential VBL of the bit line 31 causes an increase in the potential of the gate electrode of the PMOS Trp32, thereby lowering the current capacity of the PMOS Trp32. This decreases the reference voltage Vref, and accordingly, the current capacity of the NMOS Trn31 is lowered, thereby inhibiting a current from flowing into the bit line 31. As a consequence, an increase in the potential VBL of the bit line 31 is limited.
According to the above-described operation of the circuitry, the problem caused by a small transconductance gm of the NMOS Trn31 can be solved. Namely, a change in the potential VBL of the bit line 31 is maintained substantially at a constant level even if the transconductance gm of the NMOS Trn31 is small.
A description is now given of the data detecting operation performed by the above-described known current-mode sense amplifier. A current flowing in the PMOS Trp31 is indicated by Ip, a current flowing in the NMOS Trn31 is indicated by In, a current caused to flow by the memory cell 32 is represented by Imem, and a current caused to flow by the offset power supply 34 is represented by Iss.
If the current Ip is greater than the current In (Ip&gt;In), the charge supplied by a current having an amount equal to (Ip-In) is stored in the node N31. The potential VN31 of the node N31 is changed according to the amount of the stored charge. Moreover, the charge supplied by a current having an amount In-(Imem-Iss) increases the potential VBL of the bit line 31. Because of the increased potential VBL and the influence of the bias circuit 33, the current In flowing in the NMOS Trn31 is reduced.
When the current In eventually becomes equal to the sum of the currents Imem and Iss, the potential VBL of the bit line 31 is determined. When the current Ip becomes equal to the current In, the charge supply is suspended, and then, the potential VN31 of the node N31 is determined. The current In flowing in the NMOS Trn31 depends on the current capacity of the NMOS Trn31. Accordingly, the reference voltage Vref, which is applied to the gate electrode of the NMOS Trn31, is a key factor.
This is explained more specifically in the case where the high (H) level is to be extracted from the node N31. The current In becomes equal to the sum of Imem and Iss (In=Imem+Iss) more easily with a lower current capacity of the NMOS Trn31. It is thus desirable that the gate potential (reference voltage) Vref of the NMOS Trn31 is lower. On the other hand, in the case where the low (L) level is to be extracted from the node N31, the current In becomes equal to the sum of Imem and Iss (In=Imem+Iss) more easily with a higher current capacity of the NMOS Trn31. It is thus desirable that the gate potential (reference voltage) Vref of the NMOS Trn31 is higher.
For example, if the memory cell 32 causes a current to flow, it is preferable that the potential VN31 of the node N31 drops rapidly. Then, the potential VBL of the bit line 31 is lowered, which is fed back to the gate electrode of the NMOS Trn31 by the bias circuit 33, thereby elevating the gate potential Vref of the NMOS Trn31. Obviously, the circuitry is operated faster if the potential is set higher than the gate potential Vref determined by the above feedback control.
In contrast, if the memory cell 32 prevents the flowing of a current, it is preferable that the potential VN31 of the node N31 increases rapidly. Then, the potential VBL of the bit line 31 is increased, which is fed back to the gate electrode of the NMOS Trn31 by the bias circuit 33, thereby reducing the gate potential Vref of the NMOS Trn31. Clearly, the circuitry is operated faster if the potential is set lower than the gate potential Vref determined by the above feedback control.
In the known data determining circuitry described above, however, a bias voltage is obtained by using the bias circuit 33 from the data which is currently read, and based on the bias voltage, the potential VBL of the bit line 31 is controlled. It is thus difficult to set the potential higher or lower than the gate potential Vref determined by the feedback control. Particularly, if the data which is currently read is reversed with respect to the data which is read in the previous cycle, i.e., if the current data is reversed data, the data determining operation is disadvantageously delayed.